Conventional techniques of selective doping, metal deposition and photoengraving enable the mass production of such modular semiconductor units with active areas of different types and degrees of conductivity located between inactive regions along the chip surface. Emitters, bases and collectors of elemental transistors can thus be formed on the intrinsically conductive substrate and can be interlinked in part by conductor zones of predetermined resistivity (substantially less than that of the intrinsic regions) and in part by superposed metallic strips. Such strips may be used to connect respective amplifier terminals, common to all the elemental transistors, in parallel to a set of emitter, base and collector electrodes overlying the corresponding active areas of each of these transistors.
In a power amplifier of this type there are several desiderata to be satisfied, including particularly:
A. HIGH GAIN, ALSO WITH LARGE OPERATING CURRENTS;
B. LOW SATURATION VOLTAGE;
C. ABSENCE OF SECONDARY BREAKDOWNS; AND
D. COMPACT STRUCTURE.
Requirement (a) is satisfied by making the emitter area of each elemental transistor as large as possible and uniformly distributing the current density in that area at all current levels. The satisfaction of requirement (b) depends essentially on the series resistance of the collector and may be achieved by various measures such as the interleaving of the collector and emitter areas to minimize the current path therebetween. Requirement (c) can be fulfilled by a balancing of the individual emitter currents with the aid of suitably dimensioned emitter resistors formed by certain zones of the chip. Requirement (d), finally, demands a well-planned layout and optimum activation of the electrode-supporting areas of the transistor array.
In order to obtain a large emitter area with uniform current distribution, it is known to divide the transistor array into several parallel rows and to dispose a metallic emitter lead along the centerline of each row between symmetrical sets of emitter areas. A pair of such areas form part of each elemental transistor and are linked with that emitter lead by narrow conductive zones perpendicular to that lead, these zones constituting the aforementioned emitter resistors. Such a layout is satisfactory from a viewpoint of high gain at elevated current levels and, particularly with several rows of this description connected in parallel between the base and emitter terminals, also affords good utilization of the available chip surface. Within a planar array of this type, however, imbalances still exist among the elemental transistors of a row as well as among the several rows; as a result, there is no optimum utilization of the available surface area. Moreover, especially at high current levels, these imbalances may lead to local overheating entailing the risk of secondary breakdowns.